This invention relates generally to semiconductor manufacture and more particularly to an improved package for temporarily packaging semiconductor dice for testing and other purposes.
Conventionally packaged semiconductor dice are tested several times during the manufacturing process. A probe test is conducted at the wafer level to test the gross functionality of the dice. Following singulation of the wafer and packaging of the individual dice, full functionality and burn-in tests are performed on each of the packaged die. These tests are typically performed using standardized equipment that provides an electrical interface between the external contacts on the package (e.g., terminal leads) and test circuitry.
For example, burn-in ovens are adapted to hold a large number of packaged dice in a chamber with temperature cycling capability. During the burn-in test the integrated circuits are electrically tested at different temperatures. A burn-in board mountable within the chamber, includes electrical connectors that mate with the external leads on the packaged dice to establish an electrical interconnection between the individually packaged dice and test circuitry. For packaged dice having a male external contact, such as external leads formed as pins, the burn-in board may include socket connectors. For packaged dice having female external leads the burn-in board may include pogo pin connectors.
Because semiconductor dice are packaged in standardized configurations, the burn-in boards are also standardized. For example, one common semiconductor package for a single die is known as a small outline j-lead package (SOJ). A burn-in board for SOJ packages will include standardized sockets that mate with the j-leads for the packages. In addition, the spacing for the sockets will be such that a large number of packages can be mounted on a single board in a dense closely spaced array.
In addition to the boards being standardized, there is also associated equipment, such as automated handling apparatus, that is standardized for a particular package configuration. Other standardized packages for a single die include the dual in-line (DIP) package and the zigzag in-line package (ZIP).
Recently, semiconductor dice have been supplied by manufacturers in an unpackaged or bare configuration. A known good die (KGD) is an unpackaged die that has been tested to a quality and reliability level equal to the packaged product. To certify a die as a known good die the unpackaged die must be burn-in tested. This has led to the development of test carriers that hold a single unpackaged die for burn-in and other tests. Each test carrier houses a die for testing and also provides the electrical interconnection between the die and external test circuitry. Exemplary test carriers are disclosed in U.S. Pat. No. 5,302,891 to Wood et al. and U.S. Pat. No. 5,408,190 to Wood et al.
One aspect of these carriers is that they require specialized test equipment, such as specialized burn-in boards and handling equipment, that are different than the equipment used for testing conventionally packaged dice. In addition, the prior art carriers are larger than conventionally packaged dice and therefore require more and larger test equipment to achieve the same throughputs. It would be advantageous to provide a test carrier for semiconductor dice that could be used with standardized test equipment.
Another aspect of the prior art carriers for testing semiconductor dice is that the external contacts for the carriers have a limited pin out capability. Typically, the carriers include external contacts formed as pins that mate with corresponding sockets on the burn-in board. With this type of external contact configuration there may not be enough external contacts to accommodate a die having a large number of closely spaced bond pads. In general, the bond pads on semiconductor dice are becoming smaller and more densely spaced. It would be advantageous to provide a carrier for semiconductor dice having a dense external contact configuration capable of handling dice with large numbers of bond pads.
The present invention recognizes that a carrier can be constructed as a temporary package having a standard outline and external contacts arranged in a dense array. In view of the foregoing, it is an object of the present invention to provide a temporary package for semiconductor dice that can be used for testing and other purposes. It is another object of the present invention to provide a temporary package for semiconductor dice having output contacts arranged in a dense array with a high packing fraction. It is a further object of the present invention to provide a temporary semiconductor package that has a JEDEC standard outline and JEDEC standard external contact configuration. Other objects, advantages and capabilities of the present invention will become more apparent as the description proceeds.
In accordance with the present invention, an improved temporary package for a semiconductor die is provided. The temporary package has an outline and external lead configuration that matches a conventional semiconductor package. In addition, the external leads are formed in a dense array to accommodate a large number of device bond pads. Suitable dense arrays and lead configurations for the external leads can include: land grid arrays (LGA), pin grid arrays (PGA), ball grid arrays (BGA) and dense perimeter arrays. The standard outline and lead configuration of the temporary package permit standardized burn-in boards and automated package handling equipment to be used during a test procedure foreknown good die.
The temporary package includes a base, an interconnect and a force applying mechanism. The package base includes internal conductors in electrical communication with the external contacts. The package base can be formed of either ceramic or plastic. With ceramic, the package base can be formed using a ceramic lamination process or a ceramic dip formation process (Cerdip). The package base can also be formed of plastic using a 3-D injection molding process or using a ceramic dip formation (Cerdip) process combined with injection molding.
The interconnect for the package is mounted to the base and wire bonded to the conductors formed on the package base. The interconnect can be formed of silicon with raised contact members that contact and establish electrical communication with the bond pads on the die. The interconnect can also be formed with microbump contact members mounted on a plastic film similar to two layer TAB tape.
The force applying mechanism for the package includes a pressure plate, a spring and a cover. The force applying mechanism functions to secure the die within the base and to maintain the die and interconnect in electrical contact. The force applying mechanism is secured to the base with a latching mechanism.
The package is assembled by optically aligning the die and the interconnect. Prior to the alignment procedure the interconnect is mounted within the package base and wire bonded to form an electrical path between the contact members on the interconnect and the external contacts on the package base. During the alignment procedure, the die and force applying mechanism of the package can be held by an assembly tool. Flip chip optical alignment can be used to align the bond pads on the die to the contact members on the interconnect. The assembly tool then places the die on the interconnect and attaches the force applying mechanism to the package base.